High speed angle gate

ABSTRACT

A high speed angle gate for preventing the passage of an accept pulse in a seeker system if the incoming directional information is from a target outside prescribed angular limits. Two different difference amplifiers produce negative outputs when the input signal exceeds a predetermined value. The negative signal then cancels the positive enabling pulse by adding the two signals.

United States Patent Orton et al.

[451 Jan. 15, 1974 HIGH SPEED ANGLE GATE Inventors; Criley Orton,Riverside; Allen D.

Ehresman, Corona, both of Calif.

The United States of America as represented by the Secretary of theNavy, Washington, DC.

Filed: Sept. 9, 1969 Appl. No.: 857,629

Assignee:

US. Cl. 343/7 A, 343/74, 343/ 16 M Int. CL; G0ls 7/02 Field of Search343/7 A, 7.4, 16 M References Cited UNITED STATES PATENTS 6/1960 Priest343/7.4 X

Primary Examiner-T. H. Tubbesing Attorney-R. S. Sciascia, G. J. Rubensand J. W. McLaren 5 7 ABSTRACT A high speed angle gate for preventingthe passage of an accept pulse in a seeker system if the incomingdirectional information is from a target outside pre scribed angularlimits. Two different difference amplifiers produce negative outputswhen the input signal exceeds a predetermined value. The negative signalthen cancels the positive enabling pulse by adding the two signals.

3 Claims, 1 Drawing Figure DIRECTIONAL INFORMATION 2.5V Wad-Lemma O 65ACCEPTANCE GENERATOR ENABLING PULSE I PATIINIEUJAN I 5 m4 DIRECTIONALINFORMATION ENABLING PULSE 42 'M-EV 2N2222 'LI' OJMUWWANGLE SZISK 68 52ACCEPTANCE GENERATOR 5s 5.|K \N9'4 J'Ev CRILEY ORTON ALLEN D. EHRESMANINVENTORS M pi A M ATTORNEYS HIGH SPEED ANGLE GATE The invention hereindescribed may be manufactured and used by or for the Government of theUnited Statesof America for governmental purposes without the payment ofany royalties thereon or therefor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention relates to a high speed angle gate; and more particularly to ahigh speed angle gate wherein a negative pulse is produced whenever theinput amplitude (regardless of polarity exceeds the pre scribed voltagelimits,) exceeds a predetermined value.

2.3Description of the Prior Art Prior known system for high speed anglegating used numerous pulse transformers with their associated circuitrywhich was expensive and complicated.

SUMMARY OF THE INVENTION The present invention provides a high speedgating device. which prevents the passage of an accept pulse in a seekersystem if the incoming directional information iiSGfI'Om a targetoutside prescribed angular limits. Theinput signal is a bi-polardirectional information pulse whose amplitude is a measure of theangular displacement of a target from a monopulse antenna boresight. Bymeans of a difference amplifier arrangement, a negative pulse isproduced whenever the input pulse amplitude (regardless of polarity)exceeds the voltage level corresponding to the prescribed angularlimits. This negative pulse is used to cancel a positive enabling pulsetrigger so that a positive output is generated only if the input signalamplitude is less than the set voltage. The gating function can beperformed up to 200 kilohertz, over wide temperature ranges, and withlow power consumption.

BRIEF DESCRIPTION OF THE DRAWING Many of the attendant advantages ofthis invention will become readily appreciated as the same becomesbetter understood by reference to the following detailed descriptionwhen considered in connection with the accompanying drawing whereinthere is shown in a single FIGURE a schematic diagram of a preferredembodimentof the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawingthere is shown an input terminal l for receiving the directionalinformation pulses. Input terminal is connected through resistors 12 and14 to the base of transistor 16 of a different amplifier 18 for negativeinput pulses. Difference amplifier 18 includes transistors 16 and 20,clipping diode 22, emitter resistor 24 and load resistor 26.

Input terminal 10 is also connected through resistors 12 and 2810 thebase of transistor 30 of difference amplifier32 for positive inputpulses. Difference amplifier 32 includes transistors 30 and 34, clippingdiode 36, emitter resistor 38 and load resistor 40. The negative biasforthe base of transistor is supplied at terminal 42 and the positive biasfor the base of the transistor 34 issupplied at terminal 46. Thedifference between the positive bias at terminal 46 and the negativebias at terminal 42 is adjusted by variable resistor 44, and representsthe variable angle which is being accepted. The positive and negativebiases are normally symmetrical,

but occasionally are required to be unbalanced. Variable resistor 48provides the means.

Any output signal from difference amplifiers l8 and 32 are added inresistors 50 and 52 and applied to the base of transistors 54 which actsas an emitter follower. The signal across load resistor 56 is d-cdecoupled by means of capacitor 58 and blocking diode 60 and addedthrough resistor 62 to the enabling pulse applied at terminal 64 and fedthrough resistor 66. The output signal appears at terminal 68.

In operation and with the value assigned a positive input pulse atterminal 10 will be clipped at the base of transistor 16 but pulls thebase of transistor 30 positive. When the base of transistor 30 becomesas positive as the base of transistor 34 then transistor 30 beginsconducting emitter current and develops a negative-going output at itscollector. The output voltage at the collector of transistor 30 dropsfrom +12 to +6 volts during the time the positive pulse at terminal 10is present. If the input pulse at terminal 10 had been negative it wouldbe clipped at the base of transistor 30 but would cause a negative-goingpulse to appear at the collector of transistor 20 in the same mannerdescribed for difference amplifier 32. The voltage at the collector oftransistor 20 drops from 6 volts to l2 volts.

The negative-going pulses are added in resistors 50 and 52 to producepulses that drop from +3 volts to 0 volts during the time the inputpulse at terminal 10 exceeds the set limits of either polarity. Thenegative pulse appearing out of the emitter follower 54 is added to the5 volt positive enabling trigger pulse at terminal 64. The presence ofthe negative pulse out of transistor 54 is dependent upon the amplitudeof the input pulse at terminal 10 exceeding a threshold value asdetermined by the biases on transistors 20 and 34. The blocking ornon-blocking of the enabling pulse applied at terminal 64 is thendependent upon the amplitude of the input informational pulse atterminal 10.

What is claimed is:

1. In a high speed angle gate circuit, the combination comprising:

a. input terminal for receiving a bi-polar directional information pulsewhose amplitude is a measure of angular displacement,

b. difference amplifier means comprising first and second differenceamplifier coupled to said input terminal for generating an outputnegative pulse regardless of the polarlity of the input pulse wheneverthe input pulse amplitude exceeds a predetermined amplitudecorresponding to an angular limit,

c. pulse adding circuit means having a first input for receiving anegative enabling pulse and a negative input for receiving the negativeoutput pulse from said difference amplifier for cancelling said positiveenabling pulse when said negative pulse is generated.

2. The high speed gate of claim 1 wherein said first differenceamplifier has clipping means for clipping positive input pulses and saidsecond difference amplifier has clipping means for clipping negativeinput pulses.

3. The high speed gate of claim 1 wherein said difference amplifiermeans includes:

a a first difference amplifier including first and second transistorshaving a base, collector and emitter,

b the base of said first transistor being coupled to said input terminalmeans,

c the collector of said first transistor being connected to a B- voltagesupply,

(1 the emitters of said first and second transistors being connected toa B+ voltage supply,

e the collector of said second transistor being connected through a loadresistor to the B- voltage supply and f a second difference amplifierincluding third and fouth transistors having a base, collector andemitter,

g the base of said third transistor being connected to said inputterminal means,

h the collector of said third transistor being connected through a loadresistor to the B+ voltage supply,

i the emitters of said third and fourth transistors being connected tothe B- voltage supply,

j the collector of said fourth transistor being connected to the B+voltage supply,

k the collector of said second transistor being connected through addingresistors to the collector of said third transistor,

1 a voltage divider network having a first terminal connected to said Bvoltage supply and a second terminal connected to said B+ voltagesupply,

m the bases said second and fourth transistors being connected to saidvoltage divider network for providing negative and positive voltages tothe bases of said second and fourth transistors representing, re-

spectively, the lower and upper angle limits.

1. In a high speed angle gate circuit, the combination comprising: a.input terminal for receiving a bi-polar directional information pulsewhose amplitude is a measure of angular displacement, b. differenceamplifier means comprising first and second difference amplifierscoupled to said input terminal for generating an output negative pulseregardless of the polarlity of the input pulse whenever the input pulseamplitude exceeds a predetermined amplitude corresponding to an angularlimit, c. pulse adding circuit means having a first input for receivinga negative enabling pulse and a negative input for receiving thenegative output pulse from said difference amplifier for cancelling saidpositive enabling pulse when said negative pulse is generated.
 2. Thehigh speed gate of claim 1 wherein said first difference amplifier hasclipping means for clipping positive input pulses and said seconddifference amplifier has clipping means for clipping negative inputpulses.
 3. The high speed gate of claim 1 wherein said differenceamplifier means includes: a a first difference amplifier including firstand second transistors having a base, collector and emitter, b the baseof said first transistor being coupled to said input terminal means, cthe collector of said first transistor being connected to a B-voltagesupply, d the emitters of said first and second transistors beingconnected to a B+ voltage supply, e the collector of said secondtransistor being connected through a load resistor to the B- voltagesupply and f a second difference amplifier including third and fouthtransistors having a base, collector and emitter, g the base of saidthird transistor being connected to said input terminal means, h thecollector of said third transistor being connected throuGh a loadresistor to the B+ voltage supply, i the emitters of said third andfourth transistors being connected to the B- voltage supply, j thecollector of said fourth transistor being connected to the B+ voltagesupply, k the collector of said second transistor being connectedthrough adding resistors to the collector of said third transistor, l avoltage divider network having a first terminal connected to said B-voltage supply and a second terminal connected to said B+ voltagesupply, m the bases said second and fourth transistors being connectedto said voltage divider network for providing negative and positivevoltages to the bases of said second and fourth transistorsrepresenting, respectively, the lower and upper angle limits.